The present invention generally relates to a method and device for testing an integrated circuit.
For semiconductor integrated circuits, generally new chip designs have to fulfill certain electrostatic discharge criteria. For evaluating the robustness of the integrated circuits, dedicated testing is performed wherein predetermined stress signals are applied to a device under test. A stress source is used to generate the transient, which propagates from a pad or pin of the device under test to another terminal. The failures, which may occur during testing, are often only locatable with severe difficulties. In other words, thorough investigations of the damaged integrated circuits have to be performed in order to locate the defective area(s) of the integrated circuit. However, in order to design more robust structures, the knowledge about the exact location of the defects and the corresponding failure mechanism is absolutely necessary.
Electrostatic discharge (ESD) together with electrical overstress cause about 35% of all integrated circuit failures. ESD can occur for example by touching a circuit while installing it onto a printed circuit board or similar. The design efforts in order to reduce these electrostatic discharge failures amount to several million dollars a year. Besides engineer hours and the corresponding resources, material costs, for example masks, become necessary. Moreover, ESD problems often prevent short product development times.
The present invention seeks to provide to a method and device for testing integrated circuits, which mitigate or avoid problems and other disadvantages and limitations of the prior art.